Interview Bank 03 — Platform, Portability & Security (Phases 09–11)

Full answers in the phases' WARMUP Interview Q&A; this is the index + drills. These are the role's distinctive questions — the JD's core mandate + nice-to-haves.

Hardware abstraction & portability (Phase 09 — the keystone)

Q: Design a hardware-abstraction layer; walk the API/ABI boundary. Stable API (app compiles against) + backend ABI (versioned vtable + capabilities, the binary contract for separately-compiled vendor .sos) + dlopen loading (core links no backend). [P09 WARMUP Q1]

Q: How do you avoid a lowest-common-denominator abstraction? Capability negotiation: backends declare support, platform routes per workload, exposes the union, fails cleanly; operation-level abstraction + escape hatches. [P09 WARMUP Q2]

Q: How do you version a plugin ABI so a year-old backend still loads? Version-first field, append-only growth, reserved fields, flags over fields, semver with a supported range. [P09 WARMUP Q3]

Q: Build vs adopt a compiler layer? Adopt MLIR/Triton — building re-pays everything for marginal fit and slows ecosystem velocity; build your own only for a novel execution model. [P09 WARMUP Q4]

Drill: how is decoupling software from hardware a defensible business? (Inverts NVIDIA's moat; OEM backends = revenue; conformance-gated multi-vendor HAL = compounding moat. [P09 WARMUP Q5])

Observability & production ops (Phase 10)

Q: What GPU metrics do you alert on; why is "GPU utilization" misleading? utilization.gpu = "a kernel ran," not "SMs busy" — batch-1 decode shows 100% while idle. Alert on SLOs + Xid/ECC/throttle/largest-free-block. [P10 WARMUP Q1]

Q: 90% util, low throughput — investigate. Check SM-active/DRAM-active and the roofline: memory-bound decode is normal at high util; if SM-active also low, latency-bound or throttling. [P10 WARMUP Q2]

Q: Design a safe release process for a GPU serving platform. Compatibility gate (driver/CUDA/engine matrix, pre-deploy) → statistical canary → progressive rollout → auto-rollback on SLO burn → feature flags; error-budget governed. [P10 WARMUP Q3]

Drill: catch a fragmentation leak before 3am? (Alert on largest-free-block trend, distinct from cache and from a real leak. [P10 WARMUP Q4])

Drill: driver upgrade regressed 5% of the fleet — detect/respond? (Should be caught in canary; auto-rollback on budget burn; post-mortem → add SKU to canary + a perf gate. [P10 WARMUP Q5])

Security, licensing & protection (Phase 11)

Q: Design a license system for air-gapped deployment. Ed25519-signed (not encrypted) token binding features/expiry/fuzzy fingerprint, verified offline with embedded public key, bounded grace + clock-rollback resistance, challenge-response activation. State the defeat condition; private key in HSM. [P11 WARMUP Q1]

Q: Why sign instead of encrypt; where does the key live? Need integrity+authenticity not secrecy; public verifier can ship safely; encryption would put an extractable secret in the binary. Private key in HSM, the crown jewel. [P11 WARMUP Q2]

Q: Bind to specific GPUs — what about a NIC swap? GPU UUIDs + board + MAC, fuzzy N-of-M match (tolerate a swap, reject a different machine); defeat condition = fake IDs; attestation is the strong version. [P11 WARMUP Q3]

Q: Anti-tamper self-checks — what do they buy, how defeated? Catch casual patching, force the attacker to defeat the checker too; defeated by patching the checker/digest — a cost-raiser, not a guarantee. Attestation (external verifier + hardware key) is the strong answer. [P11 WARMUP Q4]

Q: Strong answer to "prove it runs unmodified on authorized hardware"? Attestation: hardware root measures code → hardware-signed quote → external verifier; the key is in hardware, below the software the attacker controls. Pair with confidential computing for weights/data. [P11 WARMUP Q5]

Drill: how is security a business enabler here? (Opens the sovereign/regulated market a cloud-assuming competitor can't serve. [P11 WARMUP Q6])

The cross-cutting synthesis question

Q: A defence ministry wants your platform on their air-gapped hardware. Design the deployment. Hardware-agnostic via the HAL (P09 — runs on whatever they have); licensed offline with challenge-response activation (P11); no phone-home, local-only observability (P10 Ch. 9); model weights protected by confidential computing + attestation-gated decryption (P11); supply-chain integrity (signed artifacts, reproducible builds) and auditability. State the honest claims (attestation proves what loaded, not bug-freeness). This threads P09+P10+P11 — the JD's sovereign-AI thesis end to end.