Lab 03 — On-Device Profiling
Phase: 06 — Qualcomm NPU Hardware & Deployment | Difficulty: ⭐⭐⭐⭐⭐ | Time: 3–4 hours
Understanding performance bottlenecks requires reading profiling traces from the NPU/DSP timeline.
What you build
- Parse simulated Snapdragon profiler JSON output
- Build a roofline model for NPU (compute-bound vs memory-bound classification)
- Identify bottleneck layers from profiling data
- Generate optimization recommendations: quantization, op fusion, layout
Key concepts
| Concept | What to understand |
|---|---|
| Roofline model | Peak TOPS vs memory BW — which resource is the bottleneck? |
| Arithmetic intensity | FLOPS / bytes moved — must exceed ridge point for compute-bound |
| HTA (Hexagon Tensor Accelerator) | Qualcomm's NPU — operates on INT8/INT4 fixed-point |
| DSP vs NPU | Some ops run on HVX DSP (vector); others on HTA (tensor) |
Files
| File | Purpose |
|---|---|
lab.py | Stubs with TODO markers |
solution.py | Complete working implementation |
test_lab.py | pytest suite |
requirements.txt | Dependencies |
Run
pip install -r requirements.txt
python lab.py
pytest test_lab.py -v